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XS1-L02A-QF124-I4 Datasheet

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XS1-L System Specification
2008/08/25
Authors:
D
M
AVID
AY
A
D
LI
IXON
A
O
YEWIN
UNG
H
M
ENK
ULLER
M
L
ARK
IPPETT
Copyright © 2008, XMOS Ltd.
All Rights Reserved
(V
0.9)
ERSION
Specifications of XMOS XS1-L02A-QF124-I4
Features:
-
Mounting Type:
Surface Mount
Package / Case:
124-TFQFN Exposed Pad
Processor Type:
XCore 32-Bit
Series:
-
Speed:
400MHz
Voltage:
0.95 V ~ 1.05 V
Other Names:
880-1005, XS1-L02-FB144-I4

Summary of Contents

Page 1

... XS1-L System Specification 2008/08/25 Authors AVID IXON A O YEWIN UNG H M ENK ULLER M L ARK IPPETT Copyright © 2008, XMOS Ltd. All Rights Reserved (V 0.9) ERSION ...

Page 2

... It is related to the L1, L2, and L4 processors which are single, dual, and quad core. The XS1-G4, and XS1-G2 specification can be found in the XS1-G System Specification document. The core archi- tecture (instruction set) specification can be found in the XS1 Instruction Set Architecture document. 2 Booting the XS1-L The standard boot procedure is to fi ...

Page 3

... If field-upgradeable firmware is required, a small boot-loader should be stored in the first sector of flash memory, followed by two boot-images starting on sector boundaries. The boot-loader should be written to read the first image initially, and on CRC failure boot from the second image. On upgrade, the first image XS1 YSTEM PECIFICATION 4 bytes ...

Page 4

... In systems where the HELLO message could be missed by the core that is trying to send out boot code, it should not send 0xzzzz0002 but a /dev/null channel identifier. Then the boot-code should resend a HELLO message to open the downstream channel. XS1 YSTEM PECIFICATION (0 ...

Page 5

... As far as a program is concerned, communication always takes place between two channel ends. A channel end is a physical resource that is allocated on the XCore Channels-ends reside on a tile and are identified by means of an identifier on the tile, a tile-identifier, and a node-identifier. Data is transmitted to a channel XS1 YSTEM PECIFICATION (0 ...

Page 6

... The sections below define the protocol layers bottom up: physical layer (Sec- tion 3.1), link layer (Section 3.2), switch layer (Section 3.3), physical layer (Sec- tion 3.1), processor communication (Section 3.5), and channel communication (Section 3.6). A summary is provided in Figure 1. XS1 YSTEM PECIFICATION (0.9) ...

Page 7

... Physical layer LLink communication uses a transition-based non return-to-zero signalling scheme. Bits are sent at a rate derived from the XS1 clock; this rate can be programmed to meet applications requirements. All links have a weak pull down, but an ex- XS1-L S ...

Page 8

... Set wire 0 to low (signals a zero in bit 1) 8. Set wire 1 to low (signals a one in bit 0) 9. Set wire 1 to high (signals control token) 10. Set wire 1 to low (terminate transmission - both wires are in rest state) XS1 YSTEM PECIFICATION (0 ...

Page 9

... For example, to send control token 0x09, transmit the following: 1. Set wire 0 to high (signals 00 bits in bits 5 and 4) 2. Set wire 2 to high (signals 10 bits in bits 3 and 2) 3. Set wire 1 to high (signals 01 bits in bits 1 and 0) XS1 YSTEM PECIFICATION ...

Page 10

... The two v transitions are chosen to return the final two wires to low. For example, to send an end-of-message after the control token sent earlier (wires 0, 1, 2, and 4 are high), transmit the following: 1. Set wire 4 to low (signals an escape). XS1 YSTEM PECIFICATION ...

Page 11

... The PAUSE and END tokens are application level control tokens, and their en- codings for higher levels are discussed in Section 3.6.1. 3.1.3 XS1-L Physical layer configuration Bits are transmitted at a speed that is set under software control. Both speed and width are set by writing to the Links speed register. Each of the speed reg- isters specifi ...

Page 12

... Mbits/second. The actual speed that can be achieved depends on the electrical characteristics of the physical connection. Note that the XS1-L cannot receive bits faster than half the switch clock rate. When two XS1-Ls are running at the same clock, they should set their inter symbol delay to at least 2. If one of the XS1-Ls has a lower switch-clock-speed, the other one should adjust its inter symbol rate accordingly ...

Page 13

... HELLO signals that this side is ready to receive credits. It requests that the other side clears its issued-counter, and issues credits. NOTE: The HELLO token is not compatible with the XS1-G. The definition of the three hardware control tokens used at the link layer is: ...

Page 14

... Initialising a LLink comprising master and slave domains If a master is controlling the power-supply of one or more slave-nodes, the mas- ter knows that the slave known state when booted. When the master knows that the slave will enable the link and issue a HELLO. XS1 YSTEM PECIFICATION (0 ...

Page 15

... XS1-L Llink Layer configuration Before a link can be used it must be enabled and a HELLO must be issued. These actions are performed by writing a 1 to the appropriate bit in the speed registers (details are shown in Section 9 ...

Page 16

... The number of bits used to identify the core on the switch depends on the number of cores attached to the switch XS1-L there is only one core and no bits are required, leaving all 16 bits to identify the switch. In the case of four cores on a switch, the lowest two bits of the address are used to identify the core, and the highest 14 bits are used to identify the switch ...

Page 17

... This mechanism enables system designers to construct the routing tables for meshes, pipelines or hypercubes. The node identifier of the XS1-L is initialised by writing its value in 15 ... 0 of the node identifier register. The most significant 16 bits are ignored. Each link can be associated with one of four logical networks by writing the network number to bits 5 ... 4 of the link’ ...

Page 18

... Figure 3 Example: configuring a pipeline of four pipelines of four XS1-L1s 3.3.3 XS1-L Switch Layer configuration The core in the XS1-L is connected to the switch by four internal links, and the switch also allows connection to other chips via eight LLinks. The switch fully connects its 12 links (four internal links and eight LLinks) and can support 12 ...

Page 19

... LLinks, and set the routing strategy. Sec- tion 9.3 summarises the registers (and the fields within the registers) that must be initialised in order to use the switch. The addresses used in the configuration messages are the register numbers of the 32-bit registers in the switch. XS1 YSTEM PECIFICATION (0.9) 18/40 ...

Page 20

... Two bytes identifying core that reply should go to One byte identifying Channel-end for reply Two bytes identifying address within switch (address[15 ... 8], address[7 ... 0]) Four bytes data to be written (data[31 ... 24], data[23 ... 16], data[15 ... 8], data[7 ... 0]) END control token (value (0x01) XS1 YSTEM PECIFICATION (0.9) 19/40 ...

Page 21

... The four privileged tokens used to control the switch are defined as follows: Name Value Description WRITEC 0xc0 Write control register READC 0xc1 Read control register PSCTRL 0xc2 PSwitch configuration message SSCTRL 0xc3 SSwitch configuration message XS1 YSTEM PECIFICATION (0.9) 20/40 2008/08/25 ...

Page 22

... Application Tokens Application tokens are defined by the compiler or application program. Four Application Control Tokens have been predefined, which should not be used for any other purpose: XS1 YSTEM PECIFICATION (0.9) 21/40 ...

Page 23

... CALL 0x8a Call code at the specified address. 3.6.2 XS1-L Configuration messsages over channels To send configuration messages over a channel, the channel needs to be con- figured to transmit messages to the SSCTRL or PSCTRL logic. The destination of a configuration message is specifi configuration resource identifier; ...

Page 24

... GETR r5, 2 SETD r5, r0 OUTCTI r5, 0xC0 OUTT r5, r11 OUTT r5, r11 SHR r1, r0, 8 OUTT r5, r1 XS1 (0.9) YSTEM PECIFICATION // preload0 // Get a channel end // set dest of chan end to SSwitch // WRITEC token // return address: node 0 // return address: processor 0 // return address: chan-id stored in r0 23/40 2008/08/25 ...

Page 25

... PSCTRL or SSCTRL), and the most significant 16 bits are the core and processor identifier. XS1 YSTEM PECIFICATION ...

Page 26

... XMOS 4 Selecting the oscillator frequency The XS1-L needs an oscillator as a clock source. It can work using clocks in the range of 4.23 MHz to 100 MHz. Internally, a PLL is used to increase the clock frequency to 400 MHz; this is the core frequency used to run the processor data path and the switch. The 400 MHz is divided derive the 100 MHz reference clock ...

Page 27

... Sleep mode, where the core voltage is removed. 5.1 Active and standby mode The XS1-L can be set to consume less dynamic power by reducing the clock frequency. When running at reduced clock frequency the XS1 standby mode, when running at full clock frequency the XS1 active mode. ...

Page 28

... SSWITCH CLK DIVIDER. Changing the clock speed of the switch affects the maximum speed at which data can be received and the speed at which data is transmitted (because the symbol-intervals and token-intervals that govern the transmission data-rate are measured in divided clock-ticks). XS1 YSTEM PECIFICATION Port synchr ...

Page 29

... Figure 4). Users of the sleep mode should note the following: For minimal leakage, when the XCore is switched off, the internal pull- downs on IO pads cannot be relied on. The system should maintain all I/O XS1 YSTEM PECIFICATION IO VDD 3.3v 1V SS_ENABLE SS_CLK XS1 device (0.9) 28/40 2008/08/25 ...

Page 30

... The wake-up counter counts at the external oscillator frequency. On wake-up the chip is brought up from power-on reset, which may take x s. Figure 5 shows the state machine of the XCore entering and leaving sleep mode. XS1 YSTEM PECIFICATION VDDCnt ! 0 VDDCnt 0 ...

Page 31

... It is recommended that the pulse width of SS ENABLE is a minimum of two SS CLK cycles plus the additional cycles to accomodate the core clock resyn- chronisation of the external wakeup condition signal and the user instructions between ISA test and the assertion of sleep. XS1 YSTEM PECIFICATION ...

Page 32

... Run the scan chain through the switch. Run the scan chain through neither (bypass). The state of the MUX is programmed over JTAG. This enables a XS1- constructed by chaining four XS1-L1s, whilst keeping the scan chain short. The MUX values are: 0000 NC The TMS signal is only connected to the MUX controller ...

Page 33

... XMOS 7 Free running oscillators There are four free-running oscillators on the XS1-L. These free-running oscilla- tors are designed to operate at different frequencies. The oscillators clock four counters. The counters and oscillators are controlled using a processor status register (using SETPS on register 6). The counter values can be read using four separate processor status registers (using GETPS on registers 7-10). Oscillators can be enabled (started) by writing a ’ ...

Page 34

... The OTP memory is programmed using three special I/O ports: the OTP address port is a 16-bit port with resource ID 0x100002XX, the OTP data is written via a 32-bit port with resource ID 0x200001XX, and the OTP control 16-bit port with ID 0x100003XX. [to be provided - guide to programming the OTP] XS1 YSTEM PECIFICATION (0.9) ...

Page 35

... XMOS 9 General configuration registers The XS1-L has three types of control registers: registers in the processor itself - control information private to the proces- sor. The registers are accessed using GETPS and SETPS instructions. registers in the processor switch - control information specifi proces- sor that can also be accessed by other processors. • ...

Page 36

... XS1 YSTEM PECIFICATION Contents RW Address of RAM. Keep at 0x00010000. RW Base of all 0 resource vectors. Used for both events and interrupts. Bits 31-16 should be set, bits 15-0 should be kept 0. RW General control bit 0: (verif) Reference clock from core clock ...

Page 37

... PS DBG DWATCH ADDR2 DRW 0x70-0x73 PS DBG DWATCH CTRL 0x80-0x83 PS DBG RWATCH ADDR1 DRW 0x90-0x93 PS DBG RWATCH ADDR2 DRW 0xA0-0xA3 PS DBG RWATCH CTRL XS1 YSTEM PECIFICATION Contents DRW Saved SR for debug interrupts DRW Saved PC for debug interrupts DRW Stores the stack pointer during ...

Page 38

... Internal link status Internal LinkPA, PB, PC PD, see Section 9.4. Ver- ification only. 0x20-0x27 Scratch register for debug software protocols 0-7 0x40-0x47 Copy of the PC of threads 0-7 0x60-0x67 Copy of the SR of threads 0-7 0x80-0x9F LLink status of LLINK 0-31, see Section 9.4. Verification only. XS1 YSTEM PECIFICATION (0.9) 37/40 8 2008/08/25 ...

Page 39

... PLL clock, ref pll (n 1). Keep at 3 for 100 MHz. 0x0C Directions for bits bits 3..0: Direction for bit 0 bits 7..4: Direction for bit 1 ... bits 31..28: Direction for bit 7 0x0D bits 3..0: Direction for bit 8 bits 7..4: Direction for bit 9 ... bits 31..28: Direction for bit 15 XS1 YSTEM PECIFICATION (0.9) 38/40 2008/08/25 ...

Page 40

... Enable link 0xA0-0xA7 LLink 0-7 static forwarding header bit 7 ... 0: Channel end bit 15 ... 8: Core identifi XS1-L) bit 31: enable static forwarding 9.4 Link status/control bit formats The LLinkand internal link registers have the following structure - where the Di- rection bits are 0 for internal links and LLinks. ...

Page 41

... XMOS Ltd makes no representation that the Information, or any particular implementa- tion thereof will be free from any claims of infringement and again, shall have no liability in relation to any such claims. (c) 2008 XMOS Limited - All Rights Reserved XS1 YSTEM PECIFICATION (0.9) ...

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